Most PCB designs start out with a correct and verified schematic in hand. The hard work of then converting the schematic design into a final PCB must then be undertaken. Quite often, the PCB will fail to workeven though the original circuit design has been undertaken with care. Even if a schematic has been verified using a simulation, what the simulation of the design fails to account for is that the specifics of the PCB layout can insert unforeseen sources of error into a design implementation. This is especially true when it comes to using newer and higher speed components with their associated higher clock speeds in a design. Additionally, data transfer speeds between devices are also continually increasing and subject to the same types of error sources. These speed increases allow for small capacitance and inductance values inherent in PCB layouts to cause the PCB implementation of a design to fail.
Along with making sure that a PCB is functional, additional requirements with regards to your designs tolerance of radiated noise and the amount of radiated noise it contributes are of great importance to getting a final design approved. As such, when developing your next PCB application that includes high speed signals, great care must be taken to mitigate electromagnetic interference issues.
Examples of high speed signals include clock signals and high speed communication ports. With some simple rules, your next design's signal integrity and electromagnetic interference levels can be improved - no need for complex mathematical models or involved and expensive simulation tools. This article will present a number of these simple rules which can be followed to insure the success of your next design with high speed signals.
Background
In this section we will discuss some of the sources of high speed layout errors and related concepts, with the next section supplying general rules to mitigate these sources of errors.
1. Electromagnetic Interference and Electromagnetic Compatibility
Electromagnetic interference is radio frequency noise that interferes with the operation of a device. On the other hand, electromagnetic compatibility refers limiting the levels of electromagnetic interference that a device emits. All devices emit some degree of electromagnetic interference and at the same time absorb some amount of electromagnetic interference. The goal of a PCB designer should be to reduce both quantities to reasonable levels. It is also of note that there are established FCC and CISPR standards for the level of EMI that devices are permitted to emit.
2. Clock Signals
Clock signals, commonly used to drive microprocessors and communication ports, should be a perfect square wave but they are not in reality. They are in fact a combination of signals at the nominal clock frequency and the harmonic frequencies above the clock frequency. As such, the EMI must be considered at both the frequency of the clock used in a design and the harmonics of the clock frequency above the nominal clock frequency.
3. Transmission Lines
At higher frequencies, transmission line effects start to come into play even on the PCB board level. Whenever the frequency of a signal line causes said signal to have a wave length on the order of the associated PCB trace, the characteristic impedance of the trace should be considered in order to prevent reflections due to impedance mismatches. In the most general sense, the PCB designer must take the time to match the impedance of the traces associated with the transceivers those traces are connecting. Using a micro strip (a trace of a defined width over a power plane) or a stripline (a trace of a defined width between two power planes) are common ways of controlling the impedance of a PCB level transmission line.
It is also common for transceivers to have high impedance inputs. In this case, the connecting trace must be terminated in way that matches the characteristic impedance of the transmission line it is connected to. There are several common termination techniques, but researching them will be left up to the reader, as they are beyond the scope of this article.
4. Crosstalk
When two traces are located next to each other, they are inductively and capacitively coupled (commonly referred to as cross talk) in a way which may allow one to compromise the operation of the other. The most basic way to eliminate this sort of noise is to separate the traces by a greater distance. Crosstalk can also be mitigated by the use of power planes to suppress crosstalk levels.
5. Differential Signals
Another way to deal with noise in a communication path is by using differential signals. Differential signals are equal and opposite in potential. Accordingly, two traces are responsible for carrying a signal between devices and the value of the signal is determined by the difference in potential on the two traces, not the absolute potential of the individual traces. This leaves differential signals immune to crosstalk and effectively immune to radiated noise.
6. Return Current and Loop Areas
When considering high frequency layouts, the return path of a signal must also be considered. When working with DC circuits, the return path will be the path of lowest resistance, but when considering AC signals the return path will be the path of lowest impedance. The result is that the return path of a high frequency signal will be directly beside the trace of said signal. Normally, the difference in return path is not a problem when the signal trace is routed over a ground plane, but it can be a problem when the ground plane is broken under the signal trace. The result is a break in the return path of the signal will be a loop. Loops are to be avoided, as they are much more effective EMI radiators and will negatively impact a design's EMC.
Practical Design Tips
Now that we have presented a brief discussion of the sources of high speed signal noise, we can move on to discuss more specific layout tips.
Before taking on your next high speed PCB design you must first take a look at the overall requirements of the design. Good questions to ask are: What is the highest frequency in the system? Will you need to use a micro strip or a stripline to achieve the level of noise suppression required by the design? What are the sensitive signals in your design? What are the minimum tolerances required by the PCB manufacturer? Are there sensitive interconnections between functional groups of the design? With these answers in hand, a general view the board stackup and composition can be determined.
1. Board Stackup
One of the most basic considerations for a new circuit design is the PCB stackup. If there are no sensitive signals to guard you may be fine using a standard 2-layer PCB. If you'e required to route signals as strip lines you will need to use a 6-layer stackup. A 4-layer PCB can also be a good intermediate option.
Another consideration is if you can create the stackup such that the power planes are very close to each other, you can reduce the need for small value decoupling capacitors to be used in your design. Finally, if you can locate the sources and sinks of you high speed signal close together on the PCB, you will be able to eliminate a major portion of the EMI and EMC related to those signals.
2. Power and Ground Planes
The most basic requirement for a high speed design is the implementation of a complete ground plane. It can also be of great benefit to include a complete power plane also, but that requires that the design be based on a four-layer or higher stackup. There is also a benefit to locate signal traces very close to power planes, which should also inform the stackup used in the final design.
When splitting parts of a power plane up, it is also important to remember that high speed signals have a return current that follows the path of lowest impedance and not resistance. Be mindful to not break up the return path of a high speed signal between its source and sink. If you must break a ground plane try not to run signal traces over this break. In the event that you do, consider reconnecting the ground plane alongside the signal trace with a 0 Ohm resistor. More succinctly, use as uniform and unbroken of ground and power planes in your design as are possible.
3. Additional Topics
Decoupling capacitors are important in creating low impedance paths to ground and power for high frequency signals. In general, you will need to use a number of different capacitor values to suppress high frequency noise across a range of frequencies. When placing capacitors, place the lowest valued capacitor closest to the device you are protecting and then proceed with larger and larger value caps. Also, make sure that the capacitor is placed between the device and the power plane that the capacitor is decoupling. This will insure that the device is in fact being decoupled by the capacitor.
Other general tips include:
• Rounding trace corners can reduce the level of EMI radiated by a signal. This is because the abrupt changes in the traces lead to higher levels of capacitance and also cause high speed signal reflections.
• To minimize crosstalk between signal traces, including those on different planes, make sure they cross each other at the right angles.
• Avoid vias in signal traces. Vias change the characteristic impedance of the trace and can cause reflections. Also, if you need to use vias with differential signal traces, consider placing them in both the traces to insure that their effect is equal in both traces.
• Consider the stub created by the use of vias. Consider using blind or burred vias in the place of conventional vias.
• Consider delays when using a distributed clock solution. Avoid branches and match trace lengths from the clock to the connected devices. It is often advisable to use a clock driver.
