When it comes to laptop PCBs, 6-layer or 8-layer circuit board is generally selected. Based on cost consideration, however, 6-layer PCB is an optimal selection for PCB designers. Sadly, EMC (Electromagnetic Compatibility) design for 6-layer PCB has been plaguing board designers.
Laptop development design is such a complex procedure that EMC design has to be carefully considered from the beginning to the end. As a matter of fact, optimal EMC achievement depends on three key considerations that will be introduced and discussed in detail in this article.
First Consideration: Scheme Design
During the process of laptop PCB design, the first step is to implement scheme design, that is, the overall arrangement and macro distribution of products have to be determined prior to authentic development, including chip and hole positions. Then, EMC engineer will carry out EMC evaluation so as to adjust chip positions and hole requirement to make them conform to EMC requirement such as bridge positions and clock chip position and tracing. A laptop PCB sketch can be drawn in order to better carry out EMC evaluation.
EMC evaluation mainly covers the following aspects:
• Tracing position and routing. Connection wire routing between LCD and motherboard or FFC-FPC connectors' routing should be inspected.
• PCB height limit inspection. High-speed signal wires can't be arranged in zero-height area which refers to circuit board together with ambient configurations. Ambient configurations contain HDD, ODD etc.
• Enclosure shielding area inspection. High-speed signal lines can't be arranged in exposure area or area with split because they reduce shielding efficiency such as keyboard position, memory cover etc.
• Laptop cover inspection. Includes hardware cover & memory cover so that grounding point can be connected with enclosure shield for each 30mm.
• Grounding of small PCBs in each unit inspection - Perfect connection should be guaranteed between small PCBs in each unit and ground through screws so as to avoid large ground impedance and stop noise signals from radiating to space.
• Reserved grounding point should be maintained for some specialized circuits to ensure low grounding impedance.
• Power noise area inspection. Instability of power area will lead the whole design to failure or drive chips far from stability by providing instable power to each chip with disturbance generated.
• One rule with most significance is that layout of leading chips on PCB and their tracing trend should be confirmed and inspected.
Second Consideration: PCB Design
PCB design is such a significant link in EMC striving that excellent PCB design is the precondition of optimal EMC achievement. PCB design without EMC taken into consideration will undoubtedly drive a waste of money and time. The first question a PCB design should ask is how electromagnetic interference (EMI) is generated and why it is transmitted. Optimal PCB design won't be obtained unless both of questions are accurately answered. Answer to those questions will be discussed in the following part of this article. An ideal PCB design rule goes: EMC has to be considered at the beginning of design and design rationality should be stuck to. Furthermore, tracing technology with low cost is best applied. Detailed design rules for printed circuit board include:
• High-speed signal wires can't be laid under connectors and power circuit should be far from connectors.
• High-speed signal wires can't be laid at the edge of PCB on any plane and spacing between board edge and those wires should be at least 50mils.
• USB, LAN, PCI card signal wires should be far from high-speed signal wires as much as possible or protected with ground wires. Moreover, ground holes should be reasonably designed.
• High-speed signal wires should be laid in internal layers.
• Since MIC phone/head phone are analog circuits, they should be violated from other circuits as much as possible.
• Clock signal wires should be arranged in internal layers after coming from IC and should be violated from signal wires at I/O interface and other traces. Clock signal wires should be arranged near reference ground plane so that image effect can be improved. Furthermore, RC terminal connection should be available when all clock signal traces are close to clock source.
• Layout of power and ground should be as compact as possible with loop issues shrinking. Moat width between powers is 15mil with ground plane complete that contains no tracing. Split ground should be reduced since too much split will increase ground impedance.
• Reasonable application of decoupling capacitor is also a key concern in PCB design. High-speed signal wires should be prohibited from going from top layer through bottom layer and ground holes should be established in order to reduce ground impedance. Furthermore, decoupling capacitor should be added to IC terminals and each power layer. At least, decoupling capacitor position should be reserved in advance.
• Anti-EMI components should be applied suitably based on their application and pricing.
Third Consideration: PCB Inspection
First of all, one concept should be rooted in engineer's mind that impedance in free space with high frequency is 377ohm. When it comes to space radiation of ordinary EMI, because signal loop reaches a stage where it can be equivalent to space impedance, signal is radiated from space. To understand this point, it's of much necessity to pull down signal loop impedance.
To control signal loop impedance, the main method lies in signal length reduction and loop area shrinking. Besides, suitable terminal connection should be carried out to control loop reflection. As a matter of fact, one method to control signal loop lies in key signal grounding. Because tracing itself features impedance in high frequency, it's best to take advantage of ground or grounding wires to connect to ground through thru holes for a couple of times. Many such designs succeed in avoiding radiation exceeding of clock signals.
Moreover, to stop signals from going through split areas, lots of engineers partition the ground by signals but fail to remember during the process of tracing. As a result, signal loop covers a large area, increasing trace length.
When it comes to EMI transmission part, it's vital to reasonably apply bypass capacitor and decoupling capacitor. Bypass capacitor has to be arranged on chip power pins and ground wires with the smallest leads. Decoupling capacitor should be arranged at a place where current demand change is the highest in order to stop noise from coupling from power and ground wires owing to tracing impedance. Of course, magnetic can be used to absorb the noise. Inductor sometimes can be used to filter noise as well. However, it should be noticed that inductor features frequency response range and package determines its frequency response, too.
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